The present invention relates to an interconnection structure and a method for designing the same in a semiconductor integrated circuit device with an interconnection structure incorporating air gaps.
Recently, as semiconductor integrated circuits have been miniaturized, the operating speed of transistors has improved, and RC delay time of interconnection has occupied the majority of signal processing time. Accordingly, reduction of wire-to-wire capacitance is most effective in reducing the RC delay, which increases as the wire length is increased and the wiring is miniaturized. In addition, as a semiconductor integrated circuit device has been more densely integrated, the capacitance between wires disposed horizontally to a substrate has been rapidly increased as compared to the capacitance between wires disposed perpendicularly to the substrate. Specifically, the shrinkage rate of a horizontal wire-to-wire space is different from that of a perpendicular wire-to-wire space. If the design rule is reduced by one generation, the wire-to-wire space and the wire width are generally reduced to about 60-70% horizontally and to about 90% perpendicularly. Thus, the more the circuit is miniaturized, the wider the difference of the wire-to-wire spaces between the horizontal and perpendicular directions become. As a result, to suppress the increase in wire-to-wire capacitance caused by miniaturization of the semiconductor integrated circuit, techniques for reducing the dielectric constant between wires are needed.
As a known technique, a semiconductor integrated circuit with an interconnection structure incorporating air gaps that can reduce a signal delay caused by the interconnection to 40% as compared to usual techniques is being used. The interconnection structure incorporating air gaps is not a structure in which every region between wires is intentionally filled up with an insulating film, but a structure in which air gaps are formed within the insulating film by utilizing a plasma CVD film with a low coverage.
By providing such an interconnection structure incorporating air gaps to a semiconductor integrated circuit device, it is possible to reduce a real relative dielectric constant between wires significantly and also to reduce the delay time depending on the wire-to-wire capacitance to 40% as compared to usual techniques.
At present, no method for designing a semiconductor integrated circuit device suitable for the interconnection structure incorporating air gaps has been established. In the interconnection structure incorporating air gaps, if air gaps occupy too much space in each interconnect layer, the strength of the interconnection structure might not be sufficiently secured. On the other hand, in reducing the delay depending on the parasitic capacitance between wires, so long as wires are spaced apart from each other by a certain distance or more, no substantial problem occurs because the parasitic capacitance is reduced.
It is therefore an object of the present invention to provide an interconnection structure, in which the strength thereof can be maintained and the delay depending on the parasitic capacitance between wires can be reduced. It is another object of the present invention to produce a method for designing wiring to obtain the structure.
A first inventive method for designing an interconnection structure of an interconnect layer in a semiconductor integrated circuit device, includes the steps of: a) forming a first dummy pattern so that at least part of the first dummy pattern is spaced apart from an actual wiring pattern by a distance equal to or smaller than a first value; b) combining the actual wiring pattern with at least the part of the first dummy pattern, thereby forming a final wiring pattern; and c) defining a gap in the final wiring pattern with a value equal to or smaller than the first value as an air gap region, in the interconnect layer.
According to this method, when an interconnection structure is formed using the final wiring pattern, gaps with a value equal to or smaller than the first value are turned into air gap regions. Some of these gaps are located in the actual wiring pattern, some are located in the dummy pattern, and the others are located between the actual wiring pattern and the first dummy pattern. Thus, air gap regions are created so as to surround almost the entire actual wiring pattern, and a structure incorporating air gaps in which no insulating film exists between the actual wiring pattern and the dummy pattern is formed. As a result, wire-to-wire capacitance can be suppressed.
In one embodiment of the present invention, the step a) may include the sub-steps of: a1) enlarging the actual wiring pattern by the first value, thereby forming a first enlarged wiring pattern; a2) enlarging the actual wiring pattern by a second value, which is larger than the first value, thereby forming a second enlarged wiring pattern; and a3) removing part of the second enlarged wiring pattern where the first and second enlarged wiring patterns overlap each other, thereby forming the first dummy pattern. Then, the first dummy pattern can be easily formed so that at least part of the first dummy pattern is spaced apart from the actual wiring pattern by the first value or smaller, using the enlarged patterns of the actual wiring pattern.
In another embodiment, the first inventive method may include the step axe2x80x2) of forming, in the interconnect layer, a second dummy pattern at a position apart from either the actual wiring pattern or the first dummy pattern by the first value in a region where neither the actual wiring pattern nor the first dummy pattern exists, between the steps a) and b). In the step b), the actual wiring pattern and the first and second dummy patterns may be combined, thereby forming the final wiring pattern. Then, a lager number of air gap regions can be created.
In this particular embodiment, in the step axe2x80x2), it is preferable that after a simple-figure pattern made of simple figures has been formed, the actual wiring pattern and the first dummy pattern are respectively enlarged by a third value, which is larger than the first value, thereby forming a third enlarged wiring pattern, and then part of the third enlarged wiring pattern where the third enlarged wiring pattern and the simple-figure pattern overlap each other is removed, thereby forming the second dummy pattern. Then, a larger number of air gap regions can be created using the simple-figure pattern.
In still another embodiment, the first inventive method may include the steps of: axe2x80x3) forming a lattice dummy pattern between the steps a) and b); and axe2x80x2xe2x80x3) forming a separated dummy pattern by separating the first dummy pattern using the lattice dummy pattern. In the step b), the separated dummy pattern, which is part of the first dummy S pattern, and the actual wiring pattern may be combined, thereby forming the final wiring pattern. Then, the parasitic capacitance between the first wiring pattern and the first dummy pattern can be reduced. As a result, the effect of suppressing a signal delay depending on the parasitic capacitance between wires can be remarkably exhibited.
In yet another embodiment, in the step a), the first dummy pattern may be formed using the first simple-figure pattern made of simple figures. Then, air gap regions can be 1s easily created.
In this particular embodiment, the step a) preferably includes the sub-steps of: a11) forming the first simple-figure pattern; a12) enlarging the actual wiring pattern by a third value, which is larger than the first value, thereby forming a third enlarged wiring pattern; and a13) removing part of the third enlarged wiring pattern where the third enlarged wiring pattern and the first simple-figure pattern overlap each other, thereby forming the first dummy pattern. Then, the first dummy pattern can be easily formed so that at least part of the first dummy pattern is apart from the actual wiring pattern by a distance equal to or smaller than the first value, using the simple-figure pattern.
In an alternative embodiment, the step a) preferably includes the sub-steps of: a21) forming the first simple-figure pattern; a22) removing part of the first simple-figure pattern where the first simple-figure pattern and the actual wiring pattern overlap each other, thereby forming a second simple-figure pattern; a23) shrinking the second simple-figure pattern by a fourth value, thereby forming a shrunk simple-figure pattern; a24) enlarging the shrunk simple-figure pattern by the fourth value, thereby forming a third simple-figure pattern; a25) removing part of the second simple-figure pattern where the second and third simple-figure patterns overlap each other, thereby forming a fourth simple-figure pattern; a26) enlarging the fourth simple-figure pattern by a fifth value, thereby forming an enlarged simple-figure pattern; a27) enlarging the actual wiring pattern by the first value, thereby forming a first enlarged wiring pattern; a28) removing part of the enlarged simple-figure pattern where the enlarged simple-figure pattern and the first enlarged wiring pattern overlap each other, thereby forming a fifth simple-figure pattern; and a29) combining the fifth and third simple-figure patterns, thereby forming the first dummy pattern. Then, a larger number of air gap regions can be created using the simple-figure patterns.
In another alternative embodiment, in the step a), the first dummy pattern is preferably formed using a striped dummy pattern formed by separating the first simple-figure pattern into striped pieces.
In this particular embodiment, the step a) more preferably includes the sub-steps of: a31) forming the first simple-figure pattern; a32) removing part of the first simple-figure pattern where the first simple-figure pattern and the actual wiring pattern overlap each other, thereby forming the second simple-figure pattern; a33) shrinking the second simple-figure pattern in one direction by the fifth value, thereby forming a first shrunk simple-figure pattern; a34) shrinking the first shrunk simple-figure pattern in one direction by a sixth value, thereby forming a second shrunk simple-figure pattern; a35) removing part of the first simple-figure pattern where the first and second simple-figure patterns overlap each other, thereby forming a sixth simple-figure pattern; and a36) combining the sixth simple-figure pattern with the second shrunk simple-figure pattern, thereby forming the striped dummy pattern. Then, capacitance between the actual wiring pattern and the first dummy pattern can be reduced. As a result, a signal delay depending on the parasitic capacitance between wires can be effectively suppressed.
A second inventive method for designing an interconnection structure of an interconnect layer in a semiconductor integrated circuit device, includes the steps of: a) forming a dummy pattern, which is in contact with an actual wiring pattern; b) combining the actual wiring pattern with the dummy pattern, thereby forming a final wiring pattern; and c) defining a region where a gap in the final wiring pattern has a value equal to or smaller than a first value as an air gap region, in the interconnect layer.
According to this method, even in a case where a gap in the actual wiring pattern is slightly wider than the first value and, therefore, it is difficult to form a dummy pattern for creating air gap regions, a dummy pattern for creating the air gap regions can be easily formed.
In one embodiment of the present invention, the step a) may include the sub-steps of: a41) enlarging the actual wiring pattern by a seventh value, thereby forming a fourth enlarged wiring pattern; a42) shrinking the fourth enlarged wiring pattern by the seventh value, thereby forming a first wire-to-wire pattern; a43) enlarging the actual wiring pattern by an eighth value, which is larger than the seventh value, thereby forming a fifth enlarged wiring pattern; a44) shrinking the fifth enlarged wiring pattern by the eighth value, thereby forming a second wire-to-wire pattern; a45) removing part of the second wire-to-wire pattern where the first and second wire-to-wire patterns overlap each other, thereby forming a third wire-to-wire pattern; a46) enlarging the actual wiring pattern by a ninth value, which is smaller than the seventh value, thereby forming a sixth enlarged wiring pattern; and a47) taking out part of the third wire-to-wire pattern where the third wire-to-wire pattern and the sixth enlarged wiring pattern overlap each other, thereby forming the dummy pattern.
A first inventive interconnection structure of an interconnect layer in a semiconductor integrated circuit device, includes: a wiring pattern formed in the interconnect layer; a dummy pattern formed in the interconnect layer so that at least part of the dummy pattern is spaced apart from the wiring pattern by a distance equal to or smaller than a predetermined value;
an air gap region provided in each of gaps with a value equal to or smaller than the predetermined value, one of which is located in the wiring pattern, another of which is located in the dummy pattern, and still another of which is located between the wiring pattern and the dummy pattern, in the interconnect layer; and an interlevel dielectric film filling regions other than the air gap region in the interconnect layer.
In this structure, air gap regions are provided around the wiring pattern as many as possible, and thus a signal delay depending on the parasitic capacitance between wires can be reduced by using the dummy pattern.
In one embodiment of the present invention, the dummy pattern may be formed using a simple-figure pattern made of simple figures.
In another embodiment, part of the dummy pattern may be separated at regular intervals. Then, the parasitic capacitance in the wiring pattern can be reduced more effectively.
A second inventive interconnection structure of an interconnect layer in a semiconductor integrated circuit device, includes: a wiring pattern formed in the interconnect layer; a dummy pattern which is in contact with the wiring pattern in the interconnect layer and includes a gap having a predetermined value or smaller; an air gap region provided in each of gaps with a value equal to or smaller than the predetermined value, one of which is located in the wiring pattern, another of which is located in the dummy pattern, and still another of which is located between the wiring pattern and the dummy pattern, in the interconnect layer; and an interlevel dielectric film filling regions other than the air gap region in the interconnect layer.
In this structure, even in a case where a gap in a wiring pattern is slightly wider than a value that is a standard for creating an air gap region, an air gap region is created in the gap. Thus, a signal delay depending on the wire-to-wire capacitance in the interconnection can be suppressed by using the dummy pattern.